Towards High-speed ASIC Implementations of Post-Quantum Cryptography

ePrint Report: Towards High-speed ASIC Implementations of Post-Quantum Cryptography

Malik Imran, Aikata Aikata, Sujoy Sinha Roy, Samuel pagliarini

In this brief, we realize different architectural techniques towards improving the performance of post-quantum cryptography (PQC) algorithms when implemented as hardware accelerators on an application-specific integrated circuit (ASIC) platform. Having SABER as a case study, we designed a 256-bit wide architecture geared for high-speed cryptographic applications that incorporates smaller and distributed SRAM memory blocks. Moreover, we have adapted the building blocks of …

algorithms application asic case cryptography eprint report hardware high integrated circuit performance platform post-quantum post-quantum cryptography pqc quantum quantum cryptography report speed study techniques