Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning. (arXiv:2202.12029v1 [cs.CR])

Microarchitectural timing channels enable unwanted information flow across
security boundaries, violating fundamental security assumptions. They leverage
timing variations of several state-holding microarchitectural components and
have been demonstrated across instruction set architectures and hardware
implementations. Analogously to memory protection, Ge et al. have proposed time
protection for preventing information leakage via timing channels. They also
showed that time protection calls for hardware support. This work leverages the
open and extensible RISC-V instruction set architecture (ISA) to introduce the
temporal fence instruction …

prevention