SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation. (arXiv:2011.10249v2 [cs.CR] UPDATED)

Microarchitectural timing attacks are a type of information leakage attack,
which exploit the time-shared microarchitectural components, such as caches,
translation look-aside buffers (TLBs), branch prediction unit (BPU), and
speculative execution, in modern processors to leak critical information from a
victim process or thread. To mitigate such attacks, the mechanism for flushing
the on-core state is extensively used by operating-system-level solutions,
since on-core state is too expensive to partition. In these systems, the
flushing operations are implemented in software (using cache …

flush isolation processor single