Random and Safe Cache Architecture to Defeat Cache Timing Attacks

arXiv:2309.16172v2 Announce Type: replace
Abstract: Caches have been exploited to leak secret information due to the different times they take to handle memory accesses. Cache timing attacks include non-speculative cache side and covert channel attacks and cache-based speculative execution attacks. We first present a systematic view of the attack and defense space and show that no existing defense has addressed all cache timing attacks, which we do in this paper. We propose Random and Safe (RaS) cache architectures to decorrelate …

architecture arxiv attack attacks cache channel covert covert channel cs.ar cs.cr exploited information leak memory non random safe secret speculative execution