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Logistic Map Pseudo Random Number Generator in FPGA
May 1, 2024, 4:11 a.m. | Mateo Jalen Andrew Calderon, Lee Jun Lei Lucas, Syarifuddin Azhar Bin Rosli, Stephanie See Hui Ying, Jarell Lim En Yu, Maoyang Xiang, T. Hui Teo
cs.CR updates on arXiv.org arxiv.org
Abstract: This project develops a pseudo-random number generator (PRNG) using the logistic map, implemented in Verilog HDL on an FPGA and processes its output through a Central Limit Theorem (CLT) function to achieve a Gaussian distribution. The system integrates additional FPGA modules for real-time interaction and visualisation, including a clock generator, UART interface, XADC, and a 7-segment display driver. These components facilitate the direct display of PRNG values on the FPGA and the transmission of data …
arxiv cs.ar cs.cr distribution fpga function generator hdl limit map modules prng processes project pseudo-random random random number real system verilog
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