HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips. (arXiv:2209.10198v1 [cs.AR])

DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system
performance by interfering with memory accesses. As DRAM chip density increases
with technology node scaling, refresh operations also increase because: 1) the
number of DRAM rows in a chip increases; and 2) DRAM cells need additional
refresh operations to mitigate bit failures caused by RowHammer, a failure
mechanism that becomes worse with technology node scaling. Thus, …

chips dram hidden latency