High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography. (arXiv:2110.12127v2 [cs.CR] UPDATED)

This paper presents a low-latency hardware accelerator for modular polynomial
multiplication for lattice-based post-quantum cryptography and homomorphic
encryption applications. The proposed novel modular polynomial multiplier
exploits the fast finite impulse response (FIR) filter architecture to reduce
the computational complexity of the schoolbook modular polynomial
multiplication. We also extend this structure to fast $M$-parallel
architectures while achieving low-latency, high-speed, and full hardware
utilization. We comprehensively evaluate the performance of the proposed
architectures under various polynomial settings as well as in the …

accelerator applications architecture complexity computational cryptography encryption exploits fast filter hardware high homomorphic encryption latency low modular novel post-quantum post-quantum cryptography quantum quantum cryptography response speed