Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators. (arXiv:2209.03830v1 [cs.AR])

In order to mitigate the security threat of quantum computers, NIST is
undertaking a process to standardize post-quantum cryptosystems, aiming to
assess their security and speed up their adoption in production scenarios.
Several hardware and software implementations have been proposed for each
candidate, while only a few target heterogeneous platforms featuring CPUs and
FPGAs. This work presents a HW/SW co-design of BIKE for embedded platforms
featuring both CPUs and small FPGAs and employs high-level synthesis (HLS) to
timely deliver the …

design hardware software