Web: http://arxiv.org/abs/2204.11972

April 27, 2022, 1:20 a.m. | Pantea Kiaei, Yuan Yao, Zhenyuan Liu, Nicole Fern, Cees-Bart Breunesse, Jasper Van Woudenberg, Kate Gillis, Alex Dich, Peter Grossmann, Patrick Schaum

cs.CR updates on arXiv.org arxiv.org

While side-channel leakage is traditionally evaluated from a fabricated chip,
it is more time-efficient and cost-effective to do so during the design phase
of the chip. We present a methodology to rank the gates of a design according
to their contribution to the side-channel leakage of the chip. The methodology
relies on logic synthesis, logic simulation, gate-level power estimation, and
gate leakage assessment to compute a ranking. The ranking metric can be defined
as a specific test by correlating gate-level …

analysis architecture assessment channel correlation side-channel

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