Augmented Symbolic Execution for Information Flow in Hardware Designs. (arXiv:2307.11884v2 [cs.CR] UPDATED)

We present SEIF, a methodology that combines static analysis with symbolic
execution to verify and explicate information flow paths in a hardware design.
SEIF begins with a statically built model of the information flow through a
design and uses guided symbolic execution to recognize and eliminate non-flows
with high precision or to find corresponding paths through the design state for
true flows. We evaluate SEIF on two open-source CPUs, an AES core, and the AKER
access control module. SEIF can …

analysis design flow hardware information non static analysis symbolic execution verify