Abusing Cache Line Dirty States to Leak Information in Commercial Processors. (arXiv:2104.08559v2 [cs.CR] UPDATED)

Caches have been used to construct various types of covert and side channels
to leak information. Most existing cache channels exploit the timing difference
between cache hits and cache misses. However, we introduce a new and broader
classification of cache covert channel attacks: Hit+Miss, Hit+Hit, and
Miss+Miss. We highlight that cache misses for cache lines in different states
may have more significant time differences, and these can be used as timing
channels. Based on this classification, we propose a new …

abusing cache information leak processors states