Nov. 20, 2023, 2:10 a.m. | William Kosasih

cs.CR updates on arXiv.org arxiv.org

This paper investigates an emerging cache side channel attack defense
approach involving the use of hardware performance counters (HPCs). These
counters monitor microarchitectural events and analyze statistical deviations
to differentiate between malicious and benign software. With numerous proposals
and promising reported results, we seek to investigate whether published
HPC-based detection methods are evaluated in a proper setting and under the
right assumptions, such that their quality can be ensured for real-word
deployment against cache side-channel attacks. To achieve this goal, …

attack attacks cache channel counter defense emerging events hardware hope malicious monitor performance proposals results software

Consultant infrastructure sécurité H/F

@ Hifield | Sèvres, France

SOC Analyst

@ Wix | Tel Aviv, Israel

Information Security Operations Officer

@ International Labour Organization | Geneva, CH, 1200

PMO Cybersécurité H/F

@ Hifield | Sèvres, France

Third Party Risk Management - Consultant

@ KPMG India | Bengaluru, Karnataka, India

Consultant Cyber Sécurité H/F - Strasbourg

@ Hifield | Strasbourg, France