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A Comprehensive Test Pattern Generation Approach Exploiting SAT Attack for Logic Locking. (arXiv:2204.11307v2 [cs.CR] UPDATED)
June 17, 2022, 1:20 a.m. | Yadi Zhong, Ujjwal Guin
cs.CR updates on arXiv.org arxiv.org
The need for reducing manufacturing defect escape in today's safety-critical
applications requires increased fault coverage. However, generating a test set
using commercial automatic test pattern generation (ATPG) tools that lead to
zero-defect escape is still an open problem. It is challenging to detect all
stuck-at faults to reach 100% fault coverage. In parallel, the hardware
security community has been actively involved in developing solutions for logic
locking to prevent IP piracy. Locks (e.g., XOR gates) are inserted in different
locations …
More from arxiv.org / cs.CR updates on arXiv.org
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