A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations. (arXiv:2207.13358v1 [cs.AR])

The rigid interface of current DRAM chips places the memory controller
completely in charge of DRAM control. Even DRAM maintenance operations, which
are used to ensure correct operation (e.g., refresh) and combat
reliability/security issues of DRAM (e.g., RowHammer), are managed by the
memory controller. Thus, implementing new maintenance operations or modifying
the existing ones often require difficult-to-realize changes in the DRAM
interface, memory controller, and potentially other system components (e.g.,
system software), leading to slow progress in DRAM-based systems.

In …

ar autonomous case chips dram operations performance security