Novel Area-Efficient and Flexible Architectures for Optimal Ate Pairing on FPGA. (arXiv:2308.04261v1 [cs.CR])

While FPGA is a suitable platform for implementing cryptographic algorithms,
there are several challenges associated with implementing Optimal Ate pairing
on FPGA, such as security, limited computing resources, and high power
consumption. To overcome these issues, this study introduces three approaches
that can execute the optimal Ate pairing on Barreto-Naehrig curves using
Jacobean coordinates with the goal of reaching 128-bit security on the Genesys
board. The first approach is a pure software implementation utilizing the
MicroBlaze processor. The second involves …

algorithms area challenges computing fpga high novel platform power resources security study